In the fabrication of MOS semiconductor devices, refractory metal silicides are often formed in source and drain (S/D) regions and in gate regions to lower resistance of these regions and to improve electrical contacts formed therewith. Conventionally, these silicides have been formed simultaneously in gate and S/D regions using a single silicide formation process. Consequently, such conventional gate silicides and S/D silicides are roughly the same thickness, and roughly the same silicide sheet resistivity results.
While it is desirable to have as thick a silicide and as low a sheet resistivity as possible in both gate and S/D regions, competing considerations may be more important for the S/D regions. One such consideration is junction depth in S/D regions. Shallower junction depths in S/D regions are more highly desired in MOS transistors to minimize unwanted short channel effects in the transistors and prevent punch-through. Thicker silicides in S/D regions require thicker S/D junction depths. Thus, a thinner S/D junction depth forces the formation of a thinner silicide. Consequently, MOS transistors benefit from the use of thicker silicides over gate regions when compared to silicides over formed S/D regions. If the thickness of such a conventionally formed one-step silicide is optimized for gate considerations, then it exhibits an inappropriate thickness in S/D regions; and, if it is optimized for S/D considerations, it exhibits an inappropriate thickness in gate regions.
Prior schemes for increasing gate silicide thickness relative to S/D silicide thickness have undesirable consequences. For example, in such schemes a gate stack having nitride or metal layers overlying a polycrystalline silicon layer is patterned and etched prior to silicide formation. Such schemes are undesirable because straight, vertically etched gate sidewalls are difficult to form from such stacks. In addition, such schemes may add thermal oxidation stages after formation of a gate oxide. Such additional thermal oxidation stages are undesirable because they tend to distort the geometry of the gate oxide underlying a gate region. Thus, a need exists for an improved method of fabricating different thickness silicides in gate and S/D regions of a semiconductor device.